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E2G0015-17-41
Semiconductor MSM511666C/CL
Semiconductor
This version: Jan. 1998 MSM511666C/CL Previous version: May 1997
65,536-Word 16-Bit DYNAMIC RAM : FAST PAGE MODE TYPE WITH EDO (BYTE WRITE)
DESCRIPTION
The MSM511666C/CL is a 65,536-word 16-bit dynamic RAM fabricated in Oki's silicon-gate CMOS technology. The MSM511666C/CL achieves high integration, high-speed operation, and low-power consumption because Oki manufactures the device in a quadruple-layer polysilicon/single-layer metal CMOS process. The MSM511666C/CL is available in a 40-pin plastic SOJ or 44/40-pin plastic TSOP. The MSM511666CL (the low-power version) is specially designed for lower-power applications.
FEATURES
* 65,536-word 16-bit configuration * Single 5 V power supply, 10% tolerance * Input : TTL compatible, low input capacitance * Output : TTL compatible, 3-state * Refresh : 256 cycles/4 ms, 256 cycles/32 ms (L-version) * Byte write and fast page mode with EDO, read modify write capability * CAS before RAS refresh, hidden refresh, RAS-only refresh capability * Package options: 40-pin 400 mil plastic SOJ (SOJ40-P-400-1.27) (Product : MSM511666C/CL-xxJS) 44/40-pin 400 mil plastic TSOP (TSOPII44/40-P-400-0.80-K) (Product : MSM511666C/CL-xxTS-K) xx indicates speed rank.
PRODUCT FAMILY
Family MSM511666C/CL-60 MSM511666C/CL-70 Access Time (Max.) tRAC tAA tCAC tOEA 60 ns 30 ns 20 ns 20 ns 70 ns 35 ns 20 ns 20 ns Cycle Time Power Dissipation (Min.) Operating (Max.) Standby (Max.) 110 ns 120 ns 550 mW 495 mW 5.5 mW/ 1.1 mW (L-version)
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Semiconductor
MSM511666C/CL
PIN CONFIGURATION (TOP VIEW)
VCC 1 40 VSS DQ1 2 DQ2 3 DQ3 4 DQ4 5 DQ5 6 DQ6 7 DQ7 8 DQ8 9 39 DQ16 38 DQ15 37 DQ14 36 DQ13 35 DQ12 34 DQ11 33 DQ10 32 DQ9 31 NC VCC DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 DQ8 NC 1 2 3 4 5 6 7 8 9 10 NC 10 VCC 11 30 VSS 28 OE UWE 12 LWE 13 RAS 14 A0 15 A1 16 A2 17 A3 18 A4 19 VCC 20 40-Pin Plastic SOJ 29 CAS 27 NC 26 NC 25 NC 24 A7 23 A6 22 A5 21 VSS 44/40-Pin Plastic TSOP (K Type) VCC UWE LWE RAS A0 A1 A2 A3 A4 VCC 13 14 15 16 17 18 19 20 21 22
Pin Name A0 - A7 RAS CAS DQ1 - DQ16 OE LWE UWE VCC VSS NC Function Address Input Row Address Strobe Column Address Strobe Data Input/Data Output Output Enable Lower Byte Write Enable Upper Byte Write Enable Power Supply (5 V) Ground (0 V) No Connection
44 43 42 41 40 39 38 37 36 35
VSS DQ16 DQ15 DQ14 DQ13 DQ12 DQ11 DQ10 DQ9 NC
32 31 30 29 28 27 26 25 24 23
VSS CAS OE NC NC NC A7 A6 A5 VSS
Note :
The same power supply voltage must be provided to every VCC pin, and the same GND voltage level must be provided to every VSS pin.
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Semiconductor
MSM511666C/CL
BLOCK DIAGRAM
RAS CAS Timing Generator Timing Generator
8
Column Address Buffers Internal Address Counter
8
Column Decoders
Write Clock Generator
UWE LWE OE
16
Output Buffers Input Buffers
16 16
A0 - A7
Refresh Control Clock
Sense Amplifiers
16
I/O Selector
16 16 16
DQ1 - DQ16
8
Row Address Buffers
8
Row Decoders
Word Drivers
Memory Cells
VCC On Chip VBB Generator VSS
FUNCTION TABLE
Input Pin RAS H L L L L L L CAS * H L L L L L LWE * * H L H L H UWE * * H H L L H OE * * L H H H H High-Z High-Z DOUT DIN Don't Care DIN High-Z DQ Pin DQ1 - DQ8 DQ9 - DQ16 High-Z High-Z DOUT Don't Care DIN DIN High-Z Function Mode Standby Refresh Word Read Lower Byte Write Upper Byte Write Word Write --
*: "H" or "L"
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Semiconductor
MSM511666C/CL
ELECTRICAL CHARACTERISTICS
Absolute Maximum Ratings
Parameter Voltage on Any Pin Relative to VSS Short Circuit Output Current Power Dissipation Operating Temperature Storage Temperature Symbol VT IOS PD* Topr Tstg Rating -1.0 to 7.0 50 1 0 to 70 -55 to 150 Unit V mA W C C
*: Ta = 25C Recommended Operating Conditions
Parameter Power Supply Voltage Input High Voltage Input Low Voltage Symbol VCC VSS VIH VIL Min. 4.5 0 2.4 -1.0 Typ. 5.0 0 -- -- Max. 5.5 0 6.5 0.8 (Ta = 0C to 70C) Unit V V V V
Capacitance
Parameter Input Capacitance (A0 - A7) Input Capacitance (RAS, CAS, UWE, LWE, OE) Output Capacitance (DQ1 - DQ16) Symbol CIN1 CIN2 CI/O Typ. -- -- --
(VCC = 5 V 10%, Ta = 25C, f = 1 MHz) Max. 7 7 7 Unit pF pF pF
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Semiconductor DC Characteristics
Parameter Output High Voltage Output Low Voltage Input Leakage Current Condition MSM511666 C/CL-60 Min. VOH IOH = -2.5 mA VOL IOL = 2.1 mA 0 V VI 6.5 V; ILI All other pins not under test = 0 V Output Leakage Current Average Power Supply Current (Operating) Power Supply Current (Standby) Average Power Supply Current (RAS-only Refresh) Power Supply Current (Standby) Average Power Supply Current (CAS before RAS Refresh) Average Power Supply Current (Fast Page Mode) Average Power Supply Current (Battery Backup) ICC6 ICC1 ILO DQ disable 0 V VO 5.5 V RAS, CAS cycling, tRC = Min. RAS, CAS = VIH ICC2 RAS, CAS VCC -0.2 V RAS cycling, ICC3 CAS = VIH, tRC = Min. RAS = VIH, ICC5 CAS = VIL, DQ = enable RAS cycling, CAS before RAS RAS = VIL, ICC7 CAS cycling, tHPC = Min. tRC = 125 ms, ICC10 CAS before RAS, tRAS 1 ms -- 300 -- -- 95 -- -- 100 -- -- 5 -- -- 100 -- -10 10 -10 -10 10 -10 2.4 0 Max. VCC 0.4
MSM511666C/CL
(VCC = 5 V 10%, Ta = 0C to 70C) MSM511666 C/CL-70 Min. 2.4 0 Max. VCC 0.4 10 V V mA Unit Note
Symbol
10
mA
-- -- -- --
100 2 1 200
-- -- -- --
90 2 1 200 90
mA 1, 2
mA mA
1 1, 5
mA 1, 2
5
mA
1
90
mA 1, 2
85
mA 1, 3
300
mA
1, 4, 5
Notes : 1. 2. 3. 4. 5.
ICC Max. is specified as ICC for output open condition. The address can be changed once or less while RAS = VIL. The address can be changed once or less while CAS = VIH. VCC - 0.2 V VIH 6.5 V, -1.0 V VIL 0.2 V. L-version.
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Semiconductor AC Characteristics (1/2)
MSM511666C/CL
(VCC = 5 V 10%, Ta = 0C to 70C) Note 1, 2, 3 Parameter Random Read or Write Cycle Time Read Modify Write Cycle Time Fast Page Mode Cycle Time Fast Page Mode Read Modify Write Cycle Time Access Time from RAS Access Time from CAS Access Time from Column Address Access Time from CAS Precharge Access Time from OE Output Low Impedance Time from CAS Data Output Hold After CAS Low
Symbol
MSM511666 C/CL-60 Min. Max. -- -- -- -- 60 20 30 35 20 -- -- 15 15 15 15 50 4 32 -- 10,000
100,000
MSM511666 C/CL-70 Min. 120 170 30 70 -- -- -- -- -- 0 5 0 0 0 0 1 -- -- 40 70 70 20 15 10 10 55 5 40 5 20 15 70 0 10 0 10 55 35 Max. -- -- -- -- 70 20 35 40 20 -- -- 15 15 15 15 50 4 32 -- 10,000
100,000
Unit Note ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ms ms ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns 5 6 7, 8 7, 8 7 7 3 4, 5, 6 4, 5 4, 6 4 4 4
tRC tRWC tHPC tHPRWC tRAC tCAC tAA tCPA tOEA tCLZ tDOH
110 155 25 65 -- -- -- -- -- 0 5 0 0 0 0 1 -- -- 40 60 60 20 15 10 10 50 5 35 5 20 15 60 0 10 0 10 45 30
CAS to Data Output Buffer Turn-off Delay Time tCEZ RAS to Data Output Buffer Turn-off Delay Time tREZ OE to Data Output Buffer Turn-off Delay Time tOEZ WE to Data Output Buffer Turn-off Delay Time Transition Time Refresh Period Refresh Period (L-version) RAS Precharge Time RAS Pulse Width RAS Hold Time RAS Hold Time referenced to OE CAS Precharge Time (Fast Page Mode with EDO) CAS Pulse Width CAS Hold Time CAS to RAS Precharge Time RAS Hold Time from CAS Precharge OE Hold Time from CAS (DQ Disable) RAS to CAS Delay Time RAS to Column Address Delay Time RAS to Second CAS Delay Time Row Address Set-up Time Row Address Hold Time Column Address Set-up Time Column Address Hold Time Column Address Hold Time from RAS Column Address to RAS Lead Time tWEZ tT tREF tREF tRP tRAS tRSH tROH tCP tCAS tCSH tCRP tRHCP tCHO tRCD tRAD tRSCD tASR tRAH tASC tCAH tAR tRAL
RAS Pulse Width (Fast Page Mode with EDO) tRASP
-- -- -- 10,000 -- -- -- -- 40 30 -- -- -- -- -- -- --
-- -- -- 10,000 -- -- -- -- 50 35 -- -- -- -- -- -- --
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Semiconductor AC Characteristics (2/2)
MSM511666C/CL
(VCC = 5 V 10%, Ta = 0C to 70C) Note 1, 2, 3 Parameter Read Command Set-up Time Read Command Hold Time Read Command Hold Time referenced to RAS Write Command Set-up Time Write Command Hold Time Write Command Hold Time from RAS Write Command Pulse Width WE Pulse Width (DQ Disable) OE Command Hold Time OE Precharge Time OE Command Hold Time Write Command to RAS Lead Time Write Command to CAS Lead Time Data-in Set-up Time Data-in Hold Time Data-in Hold Time from RAS OE to Data-in Delay Time CAS to WE Delay Time Column Address to WE Delay Time RAS to WE Delay Time CAS Precharge WE Delay Time CAS Active Delay Time from RAS Precharge RAS to CAS Set-up Time (CAS before RAS) RAS to CAS Hold Time (CAS before RAS)
Symbol
MSM511666 C/CL-60 Min. Max. -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
MSM511666 C/CL-70 Min. 0 0 0 0 10 45 10 7 10 10 10 20 20 0 10 45 15 45 60 95 65 0 5 10 Max. -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
Unit Note ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns 11 11 9 9 10
tRCS tRCH tRRH tWCS tWCH tWCR tWP tWPE tOEH tOEP tOCH tRWL tCWL tDS tDH tDHR tOED tCWD tAWD tRWD tCPWD tRPC tCSR tCHR
0 0 0 0 10 40 10 7 10 10 10 20 20 0 10 40 15 40 50 80 55 0 5 10
10 10 10 10
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Semiconductor Notes:
MSM511666C/CL
1. A start-up delay of 100 s is required after power-up, followed by a minimum of eight initialization cycles (RAS-only refresh or CAS before RAS refresh) before proper device operation is achieved. 2. The AC characteristics assume tT = 5 ns. 3. VIH (Min.) and VIL (Max.) are reference levels for measuring input timing signals. Transition times (tT) are measured between VIH and VIL. 4. This parameter is measured with a load circuit equivalent to 1 TTL load and 50 pF. The output timing reference levels are VOH = 2.0 V (IOH = -2 mA) and VOL = 0.8 V (IOL = 2 mA). 5. Operation within the tRCD (Max.) limit ensures that tRAC (Max.) can be met. tRCD (Max.) is specified as a reference point only. If tRCD is greater than the specified tRCD (Max.) limit, then the access time is controlled by tCAC. 6. Operation within the tRAD (Max.) limit ensures that tRAC (Max.) can be met. tRAD (Max.) is specified as a reference point only. If tRAD is greater than the specified tRAD (Max.) limit, then the access time is controlled by tAA. 7. tCEZ (Max.), tREZ (Max.), tWEZ (Max.) and tOEZ (Max.) define the time at which the output achieves the open circuit condition and are not referenced to output voltage levels. 8. tCEZ and tREZ must be satisfied for open circuit condition. 9. tRCH or tRRH must be satisfied for a read cycle. 10. tWCS, tCWD, tRWD, tAWD and tCPWD are not restrictive operating parameters. They are included in the data sheet as electrical characteristics only. If tWCS tWCS (Min.), then the cycle is an early write cycle and the data out will remain open circuit (high impedance) throughout the entire cycle. If tCWD tCWD (Min.) , tRWD tRWD (Min.), tAWD tAWD (Min.) and tCPWD tCPWD (Min.), then the cycle is a read modify write cycle and data out will contain data read from the selected cell; if neither of the above sets of conditions is satisfied, then the condition of the data out (at access time) is indeterminate. 11. These parameters are referenced to the CAS leading edge in an early write cycle, and to the WE leading edge in an OE control write cycle, or a read modify write cycle.
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E2G0095-17-41H Semiconductor MSM511666C/CL
,,, , ,, , ,,,,
TIMING WAVEFORM
Read Cycle
tRC tRAS tRP RAS VIH - VIL - tAR tCRP tCSH tCRP tRCD VIH - CAS VIL - VIH - VIL - VIH - VIL - VIH - VIL - VOH - tRAD tRSH tCAS tRAL tASR tRAH tASC tCAH Address Row Column tRCS tRRH tRCH WE tAA tROH tOEA tREZ OE tRAC tCAC tOEZ tCEZ DQ VOL - Open tCLZ Valid Data-out "H" or "L"
Write Cycle (Early Write)
tRC
tRAS
tRP
RAS
VIH - VIL -
tAR
tCRP
tCRP
tCSH
tRCD
tRSH
VIH - CAS VIL - VIH - VIL - VIH - VIL -
tRAD tRAH
tCAS
tASR
tASC
tCAH
tRAL
Address
Row
Column
tWCS
WE
tWCH tWP
tCWL
tWCR
tRWL
VIH - OE VIL - VIH -
tDS
tDHR
tDH
DQ
VIL -
Valid Data-in
Open
"H" or "L"
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,,,
Semiconductor MSM511666C/CL Read Modify Write Cycle
tRWC tRAS tRP RAS VIH - VIL - tAR tCSH tCRP tCRP tRCD tRSH VIH - CAS VIL - tCAS tASR tRAH tASC tCAH VIH - Address VIL - WE OE VIH - VIL - VIH - VIL - VI/OH- Row Column tRAD tRWD tCWD tAA tAWD tCWL tRWL tWP tRCS tOEA tOED tOEH tCAC tRAC tOEZ tDS tDH DQ VI/OL- tCLZ Valid Data-out Valid Data-in "H" or "L"
10/16
Semiconductor
Fast Page Mode Read Cycle (Part-1)
Address
Fast Page Mode Read Cycle (Part-2)
Address
, ,,, , ,
MSM511666C/CL
tRASP tRP RAS VIH - VIL - tRSCD tAR tRHCP tCRP tRCD tHPC tCP tCP CAS VIH VIL - - tCAS tCAS tCAS tRAD tASR tRAH tASC tCSH tCAH tASC tCAH tASC tCAH VIH - VIL - VIH - VIL - VIH - VIL - Row Column Column Column tRCS tRRH WE tCHO tOCH tRAC tAA tOEP OE tAA tAA tOEP tOEA tCAC tCPA tDOH tCAC tOEA tOEA tOEZ tCAC tOEZ tREZ DQ VOH - VOL - tCLZ
Valid Data-out
Valid Data-out Valid* Data-out Valid* Data-out
* : Same Data,
"H" or "L"
tRASP
tRP
RAS
VIH - VIL -
tRSCD
tAR
tRHCP
tCRP
tCRP
tHPC
tRCD
tCP
tCP
CAS
VIH - VIL -
tCAS
tCAS
tCAS
tRAD
tASR
tRAH
tCSH tASC tCAH Column
tASC
tCAH
tASC
tCAH
VIH - VIL - VIH - VIL - VIH - VIL -
Row
Column
Column
tRCS
tRCS
WE
tRAC tAA
tRCH
tWPE
tAA
tAA
OE
tCPA
tOEA tCAC
tWEZ
tCAC
tCAC tDOH
tCEZ
DQ
VOH - VOL -
tCLZ
Valid Data-out
Valid Data-out
Valid Data-out
"H" or "L"
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,, , , ,
Semiconductor MSM511666C/CL Fast Page Mode Write Cycle (Early Write)
tRSCD tRASP tRP RAS VIH - VIL - tAR tCRP tRCD tHPC tHPC tCP tCP CAS VIH - VIL - tCAS tCAS tCAS tRAD tASR tRAH tCSH tASC tCAH Column tASC tCAH tASC tRSH tCAH Address VIH - VIL - VIH - VIL - VIH - VIL - VIH - VIL - Row Column Column tWCS tWCH tWCS tWCH tWCS tWCH WE OE tDHR tDS tDH tDS tDH tDS tDH DQ Valid Data-in Valid Data-in Valid Data-in "H" or "L"
Fast Page Mode Read Modify Write Cycle
tRSCD
tRASP
RAS
VIH - VIL -
tRWD
tAR
tCRP
tRCD
tCP
CAS
VIH - VIL -
tRAD
tCWD
tASR
tRAH tASC
tHPRWC
tCPWD tASC
tCAH
tCWL
tCPA tCAH
tRWL
Address
VIH - VIL -
Row
Column
Column
tRCS
tAWD
tRCS
tCWD
WE
VIH - VIL -
tRAC
tAWD
tAA
tDS tWP
tAA
tDS
tWP
OE
VIH - VIL -
tOEA
tOED
tOEH tDH
tOEA
tOED
tOEH tDH
tCAC
tOEZ
tCAC
tOEZ
DQ
VI/OH - VI/OL -
Valid Data-out
Valid Data-in
Valid Data-out
Valid Data-in
tCLZ
tCLZ
"H" or "L"
12/16
,
Semiconductor MSM511666C/CL RAS-Only Refresh Cycle
tRC RAS VIH - VIL - tRAS tRP tCRP tRPC CAS VIH - VIL - tASR tRAH Address VIH - VIL - Row tCEZ DQ VOH - VOL - Open Note: WE, OE = "H" or "L" "H" or "L"
CAS before RAS Refresh Cycle
tRC
tRP
tRAS
tRP
RAS
VIH - VIL -
tRPC
tRPC
tCP
tCSR
tCHR
CAS
VIH - VIL - VOH - VOL -
tCEZ
DQ
Open Note: WE, OE, Address = "H" or "L"
13/16
Semiconductor
Hidden Refresh Read Cycle
,,, ,, ,, ,
MSM511666C/CL
tRC tRAS tRP tRC tRAS tRP RAS VIH - VIL - tAR tCRP tRCD tRSH tCHR CAS VIH - VIL - VIH - VIL - VIH - VIL - tASR tRAH tRAD tASC tCAH Address Row Column tRCS tRAL tRRH WE tAA tROH OE VIH - VIL - tOEA tRAC tCAC tCLZ tCEZ tOEZ tREZ DQ VOH - VOL - Open Valid Data-out "H" or "L"
Hidden Refresh Write Cycle
tRC tRAS
tRP
tRC tRAS
tRP
RAS
VIH - VIL - VIH - VIL -
tAR
tCRP
tRCD
tRSH
tCHR
CAS
tASR
tRAH
tRAD tASC
tCAH
tRAL
Address
VIH - VIL - VIH - VIL - VIH - VIL - VIH - VIL -
Row
Column
tWCS
tRWL tWCH
WE
tWP
tWCR
OE
tDS
tDH
DQ
Valid Data-in tDHR "H" or "L"
14/16
Semiconductor
MSM511666C/CL
PACKAGE DIMENSIONS
(Unit : mm)
SOJ40-P-400-1.27
Mirror finish
Package material Lead frame material Pin treatment Solder plate thickness Package weight (g)
Epoxy resin 42 alloy Solder plating 5 mm or more 1.70 TYP.
Notes for Mounting the Surface Mount Type Package The SOP, QFP, TSOP, SOJ, QFJ (PLCC), SHP and BGA are surface mount type packages, which are very susceptible to heat in reflow mounting and humidity absorbed in storage. Therefore, before you perform reflow mounting, contact Oki's responsible sales person for the product name, package name, pin number, package code and desired mounting conditions (reflow method, temperature and times).
15/16
Semiconductor
MSM511666C/CL
(Unit : mm)
TSOPII44/40-P-400-0.80-K
Mirror finish
Package material Lead frame material Pin treatment Solder plate thickness Package weight (g)
Epoxy resin 42 alloy Solder plating 5 mm or more 0.49 TYP.
Notes for Mounting the Surface Mount Type Package The SOP, QFP, TSOP, SOJ, QFJ (PLCC), SHP and BGA are surface mount type packages, which are very susceptible to heat in reflow mounting and humidity absorbed in storage. Therefore, before you perform reflow mounting, contact Oki's responsible sales person for the product name, package name, pin number, package code and desired mounting conditions (reflow method, temperature and times).
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